advance information failsafe? packetclock ? global communicati ons clock generat or cy26049 -1 cypress semiconductor corporation 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07488 rev. *a revised september 8, 2003 features ? fully integrated phase-locked loop (pll) failsafe? output pll driven by a crystal oscillator that is phase-aligned with external reference two 6.312-mhz outputs from 8-khz input low-jitter, high-accuracy outputs 3.3v 5% operation 16-lead tssop benefits integrated high-performance pll tailored for telecommuni- cations frequency synthesis eliminates the need for external loop filter components when reference is off, dcxo maintains clock outputs and safe pin indicates failsafe conditions dcxo maintains continuous operation should the input reference clock fail glitch-free transition simplifies system design works with commonly available, low-cost 18.432-mhz crystal zero-ppm error for all output frequencies compatible across industry standard design platforms industry standard package with 6.4 5.0 mm 2 footprint and a height profile of just 1.1 mm logic block diagram clkb 6.312mhz xin xout iclk clka 6.312mhz safe input reference clock ( typical 8khz) external pullable crystal (18.432mhz) digital controled crystal oscillator failsafe tm control phase locked loop output dividers iclk detected
advance information cy26049- 1 document #: 38-07488 rev. *a page 2 of 6 pin configuration description cy26049-1 is a failsafe frequency synthesizer with a reference clock input and two 6.312-mhz outputs. the device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. the continuous, glitch-free operation is achieved by using a dcxo, which serves as a primary clock source. the failsafe control circuit synchronizes the dcxo oscillator with the reference as long as the reference is within the pull range of the crystal. in the event of a reference clock failure the dcxo maintains the last frequency of the reference clock. the unique feature of the cy26049-1 is that the dcxo is in fact the primary clocking source. when the reference clock is restored, the dcxo automatically resynchronizes to the reference. the status of the reference clock input, as detected by the cy26049-1, is reported by the safe pin. pin description pin number pin name pin description 1iclk reference input clock : 8khz. 2nc no connect . 3nc no connect . 4nc no connect . 5vdd voltage supply : 3.3v. 6 vss ground . 7clka clock output : 6.312 mhz. 8xin pullable crystal input : 18.432 mhz. 9xout pullable crystal output : 18.432 mhz. 10 safe high = reference iclk within range, low = reference iclk out of range . 11 vss ground . 12 vdd voltage supply : 3.3v. 13 nc no connect . 14 nc no connect . 15 clkb clock output : 6.312 mhz. 16 nc no connect . selector guide part number input frequency range outputs output frequencies cy26049zc-1 reference input clock: 8 khz crystal: 18.432-mhz pullable crystal per cypress specification 2 6.312 mhz cy26049-1 16-pin tssop top view iclk 1 16 nc nc 2 15 clkb nc 3 14 nc nc 4 13 nc vdd 5 12 vdd vss 6 11 vss clka 7 10 safe xin 8 9 xout
advance information cy26049- 1 document #: 38-07488 rev. *a page 3 of 6 absolute maximum conditions supply voltage (v dd ) ........................................?0.5 to +7.0v dc input voltage........................................ ?0.5v to v dd +0.5 storage temperature (non-condensing).....?55 c to +125 c junction temperature ................................ ?40 c to +125 c data retention @ tj=125 c..................................> 10 years package power dissipation...................................... 350 mw esd (human body model) mil-std-883.................... 2000v (above which the useful life may be impaired. for user guide- lines, not tested.) recommended pullable crystal specifications [1] parameter description comments min. typ. max. unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut ?18.432? mhz c lnom nominal load capacitance ? 14 ? pf r 1 equivalent series resistance (esr) fundamental mode ? ? 25 ? r 3 /r 1 ratio of third overtone mode esr to fundamental mode esr ratio used because typical r 1 values are much less than the maximum spec 3?? dl crystal drive level no external series resistor assumed ? 0.5 2 mw f 3sephi third overtone separation from 3*f nom high side 400 ? ? ppm f 3seplo third overtone separation from 3*f nom low side ? ? ?200 ppm c 0 crystal shunt capacitance ? ? 7 pf c 0 /c 1 ratio of shunt to motional capacitance 180 ? 250 c 1 crystal motional capacitance 14.4 18 21.6 ff recommended operating conditions parameter description min. typ. max. unit v dd operating voltage 3.15 3.3 3.45 v t ac ambient temperature (commercial temperature) 0 ? 70 c c load max output load capacitance ? ? 15 pf t pu power-up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms dc electrical specifications (commercial temp: 0 to 70c) parameter description test conditions min. typ. max. unit i oh output high current v oh = v dd ? 0.5, v dd = 3.3v (source) 12 24 ? ma i ol output low current v ol = 0.5, v dd = 3.3v (sink) 12 24 ? ma v ih input high voltage cmos levels 0.7 ? ? v dd v il input high voltage cmos levels ? ? 0.3 v dd i ih input high current v ih = v dd ?510 a i il input low current v il = 0v ? 5 10 a c in input capacitance ? ? 7 pf i dd supply current c load = 15 pf, v dd = 3.45v ? ? 30 ma ac electrical specifications (commercial temp: 0 to 70 c) parameter description test conditions min. typ. max. unit f iclk-e frequency, input clock input clock frequency, external mode ? 8.00 ? khz lr failsafe lock range [2] range of reference iclk for safe = high ?250 ? +250 ppm dc = t 2 /t 1 output duty cycle duty cycle defined in figure 1 , measured at 50% of v dd 45 50 55 % t pjit1 clock jitter; output > 5 mhz period jitter, peak to peak, 10,000 periods ? ? 250 ps rms period jitter, rms ? ? 50 ps t 6 pll lock time time for pll to lock within 150 ppm of target frequency ? ? 3 ms notes: 1. ecliptek ecx-5761-18.432m meets these specifications. 2. dependent on crystals chosen and crystal specs.
advance information cy26049- 1 document #: 38-07488 rev. *a page 4 of 6 t fs_lock failsafe lock time time for pll to lock to iclk (outputs phase aligned with iclk and safe = high) ??7s f error frequency synthesis error actual mean frequency error vs. target ? 0 ? ppm er rising edge rate output clock edge rate, measured from 20% to 80% of v dd , c load = 15pf. see figure 2 . 0.8 1.4 2 v/ns ef falling edge rate output clock edge rate, measured from 20% to 80% of v dd , c load = 15pf. see figure 2 . 0.8 1.4 2 v/ns voltage and timing definitions test circuit ordering information ordering code package type operating temperature range cy26049zc-1 16-lead tssop commercial 0 to 70c CY26049ZC-1T 16-lead tssop?tape and reel commercial 0 to 70c ac electrical specifications (commercial temp: 0 to 70 c) (continued) parameter description test conditions min. typ. max. unit t1 t2 50% 50% clk figure 1. duty cycle definition; dc = t2/t1 figure 2. rise and fall time definitions: er = 0.6 x vdd / t3, ef = 0.6 x vdd / t4 clk t3 t4 80% 20% 0.1uf vdd iclk 0.1uf vdd clka c load c load clk b 16 4 3 2 1 9 10 11 12 13 15 14 5 6 7 8 18.432 mhz
advance information cy26049- 1 document #: 38-07488 rev. *a page 5 of 6 package drawing and dimensions failsafe and packetclock are trademarks of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. 16-lead thin shrunk small outline package (4.40 mm body) z16 51-85091-**
advance information cy26049- 1 document #: 38-07488 rev. *a page 6 of 6 document history page document title: cy26049-1 failsafe ? packetclock ? global communications clock generator document number: 38-07488 rev. ecn no. issue date orig. of change description of change ** 120007 11/01/02 ckn new data sheet *a 128089 09/11/03 ija changed title to failsafe ? packetclock ? global communications clock generator from failsafe communications clock generator changed some wording of features in features and benefits column changed a few definitions in pin description table replaced recommended pullable crystal specifications table
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